1. Field of the Invention
This invention relates to the field of integrated circuit (IC) interconnections, and particularly to wireless systems and methods of effecting inter- and intra-chip interconnections.
2. Description of the Related Art
For the past three decades, the performance of ICs has depended primarily on device properties. To enhance circuit and system performance, considerable effort has been expended on improving device speed by reducing the device dimensions. This decrease in minimum feature size has led to a proportional decrease in the cross-sectional area and pitch of metal interconnects (“wires”). As a result, the parasitic resistance, capacitance and inductance associated with an IC's wires are beginning to adversely affect circuit performance, and have increasingly become a primary stumbling block in the evolution of deep sub-micron ultra-LSI (ULSI) technology. Recent studies have indicated that when feature sizes fall below 1 μm, the interconnect parasitics cause signal attenuation and dispersion in the wires, seriously hurting circuit and system performance. These problems become even more acute when the bit rate capacity exceeds ˜1016 A/l2, where A is the cross sectional area of the interconnect wiring and l is the length of the wire. The RC (or LC) time delay, IR voltage drop, CV2f power loss and crosstalk parameters of an IC's wires also become significant at higher bit rates.
For the past few years, a great deal of work has been focused on improving conventional interconnect technology by reducing the resistivity of conductors (using copper, for example) and reducing the dielectric constant of interlayer dielectric materials (by using low-K polymers, for example). Nevertheless, these evolutionary approaches may soon encounter fundamental material limits which will inhibit further feature size reductions and/or bit rate increases.